The invention relates to an integrated memory having memory cells that each include a ferroelectric memory transistor.
U.S. Pat. No. 5,541,871 describes a ferroelectric semiconductor memory whose memory cells each comprise a ferroelectric memory transistor. Ferroelectric transistors have a ferroelectric gate dielectric. By applying a voltage pulse to the control electrode of the transistor, the direction of polarization of the ferroelectric, and hence, the threshold voltage of the transistor is set. With a predetermined drain-source voltage of the transistor, a different drain current is produced depending on the threshold voltage of the transistor.
For the read-out of the memory transistors, U.S. Pat. No. 5,541,871 teaches applying a predetermined drain-source voltage to the transistor and bringing the gate of the transistor to a potential which turns the transistor on. The source-drain current that is established is subsequently detected. If a low drain current is detected, a first polarization state of the ferroelectric dielectric of the transistor gate electrode is involved. If a large drain current is detected, a second polarization state of the ferroelectric is involved. Two different logic states stored by the transistor are distinguished in this way.
U.S. Pat. No. 5,541,871 teaches that the memory cells formed by the ferroelectric memory transistors are arranged in the form of a matrix. Their source terminals are connected to source lines which run parallel in a first direction. Their drain terminals are connected to parallel drain lines which run in a second direction, perpendicular to the first direction. Their gates or control electrodes are connected to control lines which run in the second direction and have the function of word lines. Since the source lines and the drain lines run perpendicularly to one another, it is necessary, in order to avoid short circuits, that they run in different wiring planes of the memory at least in the region of their crossover. The drain terminals and the source terminals of the transistors to which these lines are connected are arranged in a substrate of the memory and thus in a common wiring plane.
It is accordingly an object of the invention to provide an integrated memory having memory cells that each include a ferroelectric memory transistor which is fabricated in a simplified manner compared with the prior art specified above.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory that includes a plurality of memory cells. Each one of the plurality of the memory cells includes a ferroelectric memory transistor with a control electrode having a ferroelectric layer that can assume at least two different polarization states. The memory includes a plurality of word lines that essentially run in a first direction, and a plurality of bit lines that essentially run in a second direction that is perpendicular to the first direction. The memory includes a plurality of control lines that essentially run in the second direction. Each one of the memory transistors includes a controllable path that connects one of the plurality of the bit lines to one of the plurality of the control lines. The control electrode of each one of the memory transistors is connected to one of the plurality of the word lines. A respective one of the plurality of the control lines is configured between two of the plurality of the bit lines and is connected to the two of the plurality of the bit lines by the controllable paths of a plurality of the memory transistors. The controllable paths of the memory transistors are configured parallel to the plurality of the bit lines and parallel to the control lines. Ones of the memory transistors that are connected to a given one of the plurality of the bit lines have common source/drain regions.
The integrated memory according to the invention has word lines which run in a first direction, and also bit lines which run in a second direction, which is perpendicular to the first direction, and control lines. A controllable path of each memory transistor in each case connects one of the bit lines to one of the control lines. The control electrode of each memory transistor is connected to one of the word lines.
Since the bit lines and control lines run in the same direction and are thus arranged parallel to one another, they can be arranged within a common wiring plane of the integrated memory. Since the terminals of the controllable path (these are the drain/source regions in a MOS transistor) are usually likewise arranged in a common wiring plane, for example in a substrate of the integrated memory, it is possible, in the integrated memory according to the invention, to arrange the bit lines and control lines in the same wiring plane as the controllable path of the transistors. This results in a space-saving, simple construction of the memory. Plated-through holes which connect different wiring planes of the memory to one another are not necessary for producing a connection between the bit lines or control lines and the associated terminals of the transistor paths to be controlled. Moreover, parallel arrangement of the bit lines and control lines results in a highly regular arrangement of the memory cell matrix.
Operation of the integrated memory can be implemented by applying a predetermined voltage to the controllable path of one of the memory transistors and activating the word line connected to this transistor. The resulting current which flows between the relevant control line and the associated bit line is subsequently detected.
In accordance with an added feature of the invention, a respective one of the control lines is arranged between, in each case, two of the bit lines, to which it is connected in each case via the controllable paths of a plurality of the memory transistors. This enables the memory to have an extremely compact construction. In this memory, a read-out of one of the memory transistors can be effected as follows: a predetermined voltage is applied between one of the control lines and the two associated bit lines, one of the word lines is activated, so that two of the memory transistors connected to the word line and the relevant control line are selected, and the respective current through these two transistors is detected.
In accordance with an additional feature of the invention, the controllable paths of the memory transistors are arranged parallel to the bit lines and control lines, in other words they also run in the second direction. Furthermore, those memory transistors which are connected to the same bit line, in each case, have common source/drain regions. This further reduces the space requirement of the integrated memory. The parallel arrangement of the bit lines and control lines means that, in the second direction, the controllable paths of any desired number of adjacent memory transistors can be connected to one another.
In accordance with another feature of the invention, the integrated memory has current detecting units, which are connected to a respective one of the bit lines, for detecting a current that flows between the control lines and the bit lines, during a read access, via the memory transistors. By virtue of the fact that a current detecting unit is assigned to each bit line in this way, a respective one of the memory cells can be read out during a read access on each of the bit lines.
In accordance with a concomitant feature of the invention, the integrated memory has at least two multiplexers and two current detecting units. Two of the bit lines which are connected to two different control lines via their memory transistors are connected to the first current detecting unit via the first multiplexer. Two others of the bit lines, which are connected via their memory transistors to the same two control lines as the first two bit lines, are connected to the second current detecting unit via the second multiplexer. The multiplexers have two operating states, in which they respectively connect one of the bit lines connected to them to the respective current detecting unit.
In this development, two bit lines are, in each case, assigned to a common current detecting unit. In the event of a read access, a selection as to which of these two bit lines is in each case intended to be evaluated by the current detecting unit is effected by means of the multiplexers. Consequently, it is possible to reduce the number of current detecting units.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in integrated memory having memory cells each having a ferroelectric memory transistor, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.